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<h3 align='center'>Equations</h3>
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********** Mapped Logic **********
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PC_en <= (NOT proc_state(0) AND state_FFd1);
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enable_IR <= (NOT proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2);
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enable_acc <= (NOT proc_state(0) AND state_FFd2);
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enable_data <= (NOT proc_state(0) AND state_FFd2);
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FDCPE_int_ack: FDCPE port map (int_ack,'0','0',int_ack_CLR,int_ack_PRE);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;int_ack_CLR <= (NOT pc_reset AND NOT is_interrupt);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;int_ack_PRE <= (NOT pc_reset AND is_interrupt);
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FDCPE_is_alu: FDCPE port map (is_alu,'0','0',is_alu_CLR,is_alu_aux/is_alu_aux_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_alu_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_alu_aux/is_alu_aux_SETF);
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is_alu_aux/is_alu_aux_SETF <= ((is_in_aux/is_in_aux_SETF.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND NOT opcode_in(2) AND proc_state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc_reset AND NOT state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND NOT opcode_in(1) AND proc_state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc_reset AND NOT state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND NOT opcode_in(0) AND proc_state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc_reset AND NOT state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND proc_state(0) AND NOT pc_reset AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	is_alu AND NOT state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(2) AND opcode_in(1) AND NOT opcode_in(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	proc_state(0) AND NOT pc_reset AND NOT state_FFd1));
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FDCPE_is_branch: FDCPE port map (is_branch,'0','0',is_branch_CLR,is_branch_aux/is_branch_aux_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_branch_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_branch_aux/is_branch_aux_SETF);
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is_branch_aux/is_branch_aux_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_branch AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_branch AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT opcode_comp_in(1) AND NOT opcode_comp_in(0)));
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is_call <= pc_reset;
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FDCPE_is_immediate: FDCPE port map (is_immediate,'0','0',is_immediate_CLR,is_immediate_OBUF/is_immediate_OBUF_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_immediate_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_immediate_OBUF/is_immediate_OBUF_SETF);
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is_immediate_OBUF/is_immediate_OBUF_SETF <= ((NOT opcode_in(3) AND NOT opcode_in(2) AND proc_state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc_reset AND NOT state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND NOT opcode_in(1) AND proc_state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc_reset AND NOT state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND NOT opcode_in(0) AND proc_state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc_reset AND NOT state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND proc_state(0) AND NOT pc_reset AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	is_immediate AND NOT state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(2) AND NOT opcode_in(1) AND opcode_in(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	proc_state(0) AND NOT pc_reset AND is_immediate AND NOT state_FFd1));
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FDCPE_is_in: FDCPE port map (is_in,'0','0',is_in_CLR,is_in_aux/is_in_aux_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_in_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_in_aux/is_in_aux_SETF);
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is_in_aux/is_in_aux_SETF <= ((opcode_in(3) AND NOT opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_in AND NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_in AND NOT state_FFd1 AND NOT state_FFd2));
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is_interrupt <= (proc_state(0) AND state_FFd2);
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FDCPE_is_jump: FDCPE port map (is_jump,'0','0',is_jump_CLR,is_jump_aux/is_jump_aux_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_jump_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_jump_aux/is_jump_aux_SETF);
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is_jump_aux/is_jump_aux_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_jump AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_jump AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_comp_in(1) AND NOT opcode_comp_in(0)));
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FDCPE_is_load: FDCPE port map (is_load,'0','0',is_load_CLR,is_load_aux/is_load_aux_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_load_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_load_aux/is_load_aux_SETF);
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is_load_aux/is_load_aux_SETF <= ((opcode_in(3) AND NOT opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_load AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_load AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2));
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FDCPE_is_mem: FDCPE port map (is_mem,'0','0',is_mem_CLR,is_mem/is_mem_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_mem_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_mem/is_mem_SETF);
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is_mem/is_mem_SETF <= ((opcode_in(3) AND NOT opcode_in(2) AND proc_state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND NOT opcode_in(1) AND opcode_in(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND is_mem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	is_mem));
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FDCPE_is_misc: FDCPE port map (is_misc,'0','0',is_misc_CLR,is_misc_aux/is_misc_aux_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_misc_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_misc_aux/is_misc_aux_SETF);
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is_misc_aux/is_misc_aux_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_misc AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_misc AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_comp_in(1) AND opcode_comp_in(0)));
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FDCPE_is_ret: FDCPE port map (is_ret,'0','0',is_ret_CLR,is_ret_OBUF/is_ret_OBUF_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_ret_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_ret_OBUF/is_ret_OBUF_SETF);
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is_ret_OBUF/is_ret_OBUF_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_ret AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_ret AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND NOT cod_ext3_in(2) AND NOT cod_ext3_in(1) AND NOT cod_ext3_in(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND opcode_comp_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_comp_in(0)));
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FDCPE_is_reti: FDCPE port map (is_reti,'0','0',is_reti_CLR,is_reti_OBUF/is_reti_OBUF_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_reti_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_reti_OBUF/is_reti_OBUF_SETF);
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is_reti_OBUF/is_reti_OBUF_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_reti AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_reti AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND NOT cod_ext3_in(2) AND NOT cod_ext3_in(1) AND cod_ext3_in(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND opcode_comp_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_comp_in(0)));
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FDCPE_is_shift: FDCPE port map (is_shift,'0','0',is_shift_CLR,is_shift_aux/is_shift_aux_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_shift_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_shift_aux/is_shift_aux_SETF);
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is_shift_aux/is_shift_aux_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	proc_state(0) AND is_shift AND NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_shift AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2));
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FDCPE_is_stdby: FDCPE port map (is_stdby,'0','0',is_stdby_CLR,is_stdby/is_stdby_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_stdby_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_stdby/is_stdby_SETF);
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is_stdby/is_stdby_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	is_stdby)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	is_stdby)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND cod_ext3_in(2) AND NOT cod_ext3_in(1) AND cod_ext3_in(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND opcode_comp_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_comp_in(0)));
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FDCPE_is_store: FDCPE port map (is_store,'0','0',is_store_CLR,is_store_aux/is_store_aux_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_store_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_store_aux/is_store_aux_SETF);
</td></tr><tr><td>
</td></tr><tr><td>
is_store_aux/is_store_aux_SETF <= ((opcode_in(3) AND NOT opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND NOT opcode_in(1) AND opcode_in(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	proc_state(0) AND is_store AND NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND is_store AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd2));
</td></tr><tr><td>
FDCPE_is_wait: FDCPE port map (is_wait,'0','0',is_wait_CLR,is_wait/is_wait_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;is_wait_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_wait/is_wait_SETF);
</td></tr><tr><td>
</td></tr><tr><td>
is_wait/is_wait_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	is_wait)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	is_wait)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND cod_ext3_in(2) AND NOT cod_ext3_in(1) AND NOT cod_ext3_in(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND opcode_comp_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_comp_in(0)));
</td></tr><tr><td>
</td></tr><tr><td>
pc_reset <= (proc_state(0) AND state_FFd2);
</td></tr><tr><td>
FDCPE_proc_state0: FDCPE port map (proc_state(0),proc_state_D(0),clk_i,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;proc_state_D(0) <= ((EXP6_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (EXP7_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (int_req AND NOT clr_i AND NOT proc_state(0) AND state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT port_ack_i AND NOT clr_i AND proc_state(0) AND state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	s_out)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (instr_ack_i AND NOT clr_i AND NOT proc_state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT port_ack_i AND NOT data_ack_i AND NOT clr_i AND NOT proc_state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	is_load AND state_FFd2 AND is_mem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (int_req AND NOT clr_i AND proc_state(0) AND NOT is_alu AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_shift AND NOT state_FFd1 AND NOT state_FFd2 AND NOT is_mem));
</td></tr><tr><td>
</td></tr><tr><td>
proc_state(1) <= ((proc_state(0) AND state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT proc_state(0) AND state_FFd2));
</td></tr><tr><td>
</td></tr><tr><td>
proc_state(2) <= NOT (((proc_state(0) AND NOT pc_reset)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT pc_reset AND NOT state_FFd1)));
</td></tr><tr><td>
</td></tr><tr><td>
reg_file_we <= (NOT proc_state(0) AND state_FFd1);
</td></tr><tr><td>
FDCPE_s_out: FDCPE port map (s_out,'0','0',s_out_CLR,s_out/s_out_SETF);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;s_out_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT s_out/s_out_SETF);
</td></tr><tr><td>
</td></tr><tr><td>
s_out/s_out_SETF <= ((opcode_in(3) AND NOT opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND s_out AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND s_out AND NOT state_FFd2));
</td></tr><tr><td>
FDCPE_state_FFd1: FDCPE port map (state_FFd1,state_FFd1_D,clk_i,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;state_FFd1_D <= ((clr_i)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (EXP9_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (proc_state(0) AND NOT state_FFd1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT proc_state(0) AND NOT state_FFd2));
</td></tr><tr><td>
FTCPE_state_FFd2: FTCPE port map (state_FFd2,state_FFd2_T,clk_i,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;state_FFd2_T <= ((EXP8_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state_FFd1.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (clr_i AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT int_req AND is_misc AND NOT state_FFd2 AND is_stdby)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT int_req AND is_misc AND NOT state_FFd2 AND is_wait)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT int_req AND NOT is_alu AND NOT is_shift AND NOT state_FFd2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT is_mem));
</td></tr><tr><td>
Register Legend:
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDCP  (Q,D,G,CLR,PRE); 
</td></tr><tr><td>
</td></tr>
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